With the scaling of transistor dimensions to smaller sizes, the variability in the number and location of dopant atoms in transistor channels may result in unwanted variations in device threshold voltage among various transistors. This may be of particular concern when using minimum geometry devices in area-limited circuits, such as Static Random Access Memory (SRAM). Mismatch in threshold voltage among neighboring devices within a SRAM cell may dramatically reduce its read stability. Read cell stability may be loosely defined as the probability that during a read operation performed upon a cell, the cell will “flip” its content. This may be explained by considering FIGS. 1a and 1b. 
A portion of a typical SRAM is shown in simplified form in FIG. 1a, and one of its 6T SRAM cells is shown in FIG. 1b. In FIG. 1a, during a pre-charge phase, pre-charge line 102 is brought LOW so that pull-up pFETs 104 and 106 charge bitlines 108 and 110 to Vcc (HIGH). During a read operation, pre-charge line 102 is HIGH so that pull-ups 104 and 106 are OFF; and one of the wordlines, say wordline WL1, is brought HIGH so that its corresponding cell, Cell1, is read. Referring to FIG. 1b, assume that node 114 is LOW to store a logical “0” and node 116 is HIGH to store a logical “1”, and that bitlines 108 and 110 have been pre-charged to Vcc. At the beginning of a read operation, wordline 112 is brought HIGH, resulting in node 114 rising above LOW (“0”) due to the voltage divider comprising access nFET 118 and pull-down nFET 120. This voltage division is between the Vcc pre-charged bitline 110 and ground node 122 (or ground rail, at voltage Vss) of the cell. If node 114 rises too high, the stored cell content may be “flipped”, resulting in an incorrect read operation.
The lower the ON-resistance of NFET 120 relative to that of access NFET 118 (commonly referred to as the cell ratio), the smaller the noise figure on the “0” node (114). A lower noise figure, other things being equal, leads to an increase in read stability. In practice, SRAM cells should be designed to meet a specified minimum cell stability. Process scaling may make it harder to achieve this because of an expected increase in device parameter variations, e.g., variations in device threshold voltage.
Various techniques have been proposed to improve cell stability in a SRAM cell. For example, the width of the pull-down nFETs may be increased, but this results in a larger cell area and may make it more difficult to perform a stable write operation. As another example, the length of the (minimum-sized) access transistor in a SRAM cell may be increased, but this leads to a reduction in channel current during a read operation, thereby decreasing speed. As another example, the strength of the pull-down nFETs in a SRAM cell may be increased by driving their source terminals to a negative voltage just before the cell's corresponding wordline is brought HIGH. This boosts the drive of the pull-down nFETs due to increasing both the gate-to-source and drain-to-source voltages. But this requires a negative supply voltage generator with its associated area and power overhead, as well as process technology for a higher gate-oxide breakdown voltage.